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In a Makefile, you can define multiple targets that share the same rule to avoid duplicating the recipe. This is useful when you have several targets that need to be built using the same set of commands.
Example
TARGETS = file1 file2 file3all: $(TARGETS)file1: dep1 dep2file2: dep2 dep3 dep4file3: dep2 dep1$(TARGETS):cat $^ > $@In this example, file1, file2, and file3 are targets with their own prerequisites. The recipe cat $^ > $@ is shared among all these targets12.
Independent Targets
When using the standard target separator :, each target is treated independently. This means that the recipe will be executed separately for each target.
bigoutput littleoutput : text.ggenerate text.g -$(subst output,,$@) > $@This is equivalent to:
bigoutput : text.ggenerate text.g -big > bigoutputlittleoutput : text.ggenerate text.g -little > littleoutputGrouped Targets
If you have a recipe that generates multiple files from a single invocation, you can use grouped targets with the separator &:.
Makefile with multiples rules sharing same recipe
Jul 11, 2012 · I'd like to know if it's possible to write a Makefile with several rules, each one defining its own prerequisites and executing all of them the same recipe without duplicating the …
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Sep 25, 2022 · Starting from GNU make-4.4 rules with multiple targets that include commands will trigger if any of the targets does not exist. This will require a few projects to adapt. Older …
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